i'm supposed write c program takes .asm file contains set of mips instructions , provides diagnostic of occurs during each cycle. far formatting, etc won't need help. i've been given code covers that; i'm struggling figuring out how set pipeline registers.
i have ifid pipeline set , think have idex pipeline set correctly i'm unsure if i'm on right track, regfile array i'm unsure about, state.regfile[(state.pc)/4]; divided 4 due fact addresses, meant mimic mips, word aligned don't know if have makes sense.
here snippet of main function.
note ifid, idex, exmem, memwb pipelines , structs each containing necessary information each pipeline.
void run(){ statetype state; /* contains state of entire pipeline before cycle executes */ statetype newstate; /* contains state of entire pipeline after cycle executes */ initstate(&state); /* initialize state of pipeline */ while (1) { printstate(&state); /* if halt instruction entering wb stage, of legitimate */ /* instruction have completed. print statistics , exit program. */ if (get_opcode(state.memwb.instr) == halt) { printf("total number of cycles executed: %d\n", state.cycles); /* remember print number of stalls, branches, , mispredictions! */ exit(0); } newstate = state; /* start making newstate copy of state before cycle */ newstate.cycles++; /* modify newstate stage-by-stage below reflect state of pipeline after cycle has executed */ /* --------------------- if stage --------------------- */ /* setting ifids instruction equal instruction found @ address state.pc*/ newstate.ifid.instr = state.instmem[(state.pc)/4]; /* setting ifid's pcplus4 state.pc + 4 */ newstate.ifid.pcplus4 = state.pc + 4; /* update pc */ newstate.pc = state.pc + 4; /* --------------------- id stage --------------------- */ newstate.idex.instr = state.instmem[(state.pc)/4]; newstate.idex.pcplus4 = state.pc + 8; newstate.idex.readdata1 = state.regfile[(state.pc)/4]; newstate.idex.readdata2 = state.regfile[(state.pc)/4]; newstate.idex.immed = state.regfile[(state.pc)/4]; newstate.idex.rsreg = state.regfile[(state.pc)/4]; newstate.idex.rtreg = state.regfile[(state.pc)/4]; newstate.idex.rdreg = state.regfile[(state.pc)/4]; newstate.idex.branchtarget = state.regfile[(state.pc)/4]; /* --------------------- ex stage --------------------- */ newstate.exmem.instr = state.instrmem[(state.pc)/4]; newstate.exmem.pcplus4 = state.pc + 12; /* --------------------- mem stage --------------------- */ /* --------------------- wb stage --------------------- */ state = newstate; /* newstate becomes old state before execute next cycle */ } }
(state.pc)/4 makes sense array index of instruction. however, not make sense index register file.
you have decode instruction, fetched in if stage. bitfields in instruction index register file. immediate doesn't come register file, comes instruction, because that's immediate means.
the instruction shouldn't re-fetched (as happens in newstate.idex.instr = state.instmem[(state.pc)/4];), because may need kill (a branch has kill @ least 1 instruction in pipeline turns out there incorrectly, 2 if don't have delay slot).
as general tip, if i'd @ pipeline diagram in book covers classic risc pipeline, example patterson & hennessy computer organization design.
i have example here, made partly me (based on existing architectures university of amsterdam) in sim-pl (which uva).
you can see here id stage doesn't use pc. passes on ex stage, calculates branch target.
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