cpu - What are shadow registers in MIPS and how are they used? -

when read mips architecture, came across shadow registers said copies of general purpose registers.

i couldn't understand following: when shadow registers used?

mips shadow registers used reduce register load/store overhead in handling interrupts. interrupt shadow register set assigned not need save of existing context provide free registers or load interrupt-specific data stored in shadow registers @ entry interrupt handler; @ exit of interrupt handler no saving of interrupt handler context or restoring of previous context necessary.

arm provides similar functionality calls banked registers. (for arm, of gprs replicated.)

the mips multithreading application specific extension extends use of shadow register sets become thread contexts. (shadow register sets in effect support limited form of switch-on-event-multithreading threads conceptually limited interrupt handlers , events interrupts.)