what significance of changing duty cycle in i2c protocol? feature available in of advanced microcontrollers.
the duty cycle significant, because different i²c modes have different duty cycle.
check i²c specification v5 table 10, pg. 48.
mode | t_high | t_low | ratio --------------+--------+-------+------- standard-mode | 4.00u | 4.7u | 0.85 fast-mode | 0.60u | 1.3u | 0.46 fast-mode plus| 0.26u | 0.5u | 0.52 your controller need decide on 1 ratio in order within i²c specification.
so instance, if controller using standard mode timing ratio, prevent achieving fast mode timings maximum clock frequency.
these ratios defined in standard minimal t_high:t_low. however, notice 100 khz period 10 us, t_high + t_low table less 10 us. thus, ratio of actual values can vary long t_high , t_low minimum timings met.
the point of these ratios illustrate i²c timing constraints different between i²c modes. aren't mandatory ratios controllers need keep.
for example, 4 high, 6 low 0.67 ratio, yet standard-mode timings met.
stm32f4 example:
the stm32f4xx series supports 100 khz , 400 khz communication speeds (rm0090, rev 5, pg. 818, section 27.2).
i don't know ratios come from, reference manual states (rm0090, rev 5, pg. 849, section 27.6.8) 1:1 ratio standard mode, , 1:2 or 9:16 ratio fast mode.
so instance, achieve highest standard mode clock frequency of 100 khz, t_high , t_low need programmed 5 us, because ratio 1:1.
for fast-mode, example 1:2 ratio, need program t_high 3.33 , t_low 6.66 100 khz. yet not meet timing requirements standard-mode.
so cannot use stm32f4 programmed fast-mode while keeping standard-mode timings @ highest standard-mode frequency.
and vice versa: cannot use standard-mode , program 400 khz fast-mode, because default 1:1 ratio out-of-spec 2.5 us, because t_low 1.25 < 1.3 us.
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