system verilog - SystemVerilog name alias -

does systemverilog enables aliases module instances , enumerations? eg, how code this:

enum logic {foo, bar} myenum enum logic {baz, qux} myenum 

ie, baz , qux aliases of foo , bar respectively.

the let construct can expression

enum logic {foo, bar} myenum let baz = foo; let qux = bar; 

you cannot alias instance name.