Bidirectional port in verilog testbench -

how assign input bidirectional port in verilog testbench ?

i have design , associated testbench. relevant part of design follows:

module i2cmodule ( input   wire        mod_en ,  input   wire        rec_ack , input   wire        burst_write , burst_read , input   wire        [7 : 0] data_tx ,    output  wire        [7 : 0] data_rx ,    output  wire        ack , inout   wire    scl , inout   wire    sda  ) ;  // code here  send_command :     begin            case (bit_counter)          // parallel serial convertor             7   : sda_reg = ( !scl) ? data_tx[7] : sda_reg ;             6   : sda_reg = ( !scl) ? data_tx[6] : sda_reg ;             5   : sda_reg = ( !scl) ? data_tx[5] : sda_reg ;             4   : sda_reg = ( !scl) ? data_tx[4] : sda_reg ;             3   : sda_reg = ( !scl) ? data_tx[3] : sda_reg ;             2   : sda_reg = ( !scl) ? data_tx[2] : sda_reg ;             1   : sda_reg = ( !scl) ? data_tx[1] : sda_reg ;             0   : sda_reg = ( !scl) ? data_tx[0] : sda_reg ;         endcase          start_bit_counter = (scl && !bit_counter) ? 1'b0 : start_bit_counter ;         i2c_next = (!start_bit_counter) ? wait_ack : send_command ;     end      wait_ack :     begin         ack_reg = ( scl) ? sda : ack_reg ;         start_bit_counter = ( scl) ? 1'b1 : 1'b0 ;         i2c_next = (scl && !ack_reg) ? (data_tx[7] ? rx_mode : tx_mode ) : wait_ack ;     end  // code here 

testbench follows:

module i2c_test;  // inputs reg mod_en; reg rec_ack; reg burst_write; reg burst_read; reg [7:0] data_tx;  // outputs wire [7:0] data_rx; wire ack;  // bidirs wire scl; wire sda;  // stimulus here ; stimulus in initial block      mod_en = 1 ;     data_tx = 8'b10101010 ;             // write mode     repeat (8) @ (posedge scl) ;    // wait 8 clocks command sent     sda = 1'b0 ;                                            // slave ack     @ (posedge scl) ; 

the design synthesizes target device. however, in testbench, when try drive sda, gives error. also, if change sda reg, says outputs cannot reg type.

how drive sda in testbench?

if need drive bidir signal module or test bench, can this:

wire [7:0] input_value; wire [7:0] bidir_signal; reg [7:0] output_value; reg output_value_valid;  mymodule myinstance (   ...   ...   .bidir_signal(bidir_signal),   ...   ... );  assign input_value = bidir_signal; assign bidir_signal = (output_value_valid==1'b1)? output_value : 8'hzz;  initial begin   output_value_valid = 0;   // use bidir_signal input here can read current value   //   $display ("current value: %x\n", input_value);   #100;   // switch output signal: write value 10101010 in   output_value_valid = 1;   output_value = 8'haa;   #100;   $finish; end