synthesis - Verilog HDL: Having nested if inside reset condition is synthesizable? -

always @ (posedge clock or negedge reset_l)   //active low asyn reset begin     if(!reset_l)     begin         if(enable)         begin             status <= 1'b0;         end     end     else     begin         if(enable)         begin             status <= 1'b1;         end     end end 

i running synthesis using synopsis design compiler. getting warning @ line 5 enable read not mentioned in sensitivity list.

my doubt can reset if-loop can have nested if's ?

don't - if reset_l active, , enable not active, clock ignored though device isn't being reset. shouldn't synthesise, , gate-level , rtl sims won't match if does. how recoding:

   assign rst2 = !reset_l & enable;    @(posedge clock or posedge rst2)      if(rst2)        status <= 0;      else if(enable)        status <= 1;