i have seen example written in vhdl file
example snippet,
architecture aaa of bbb signal ccc : std_logic begin ccc <= transport global_en_lb; .... i want know transport in above snippet. means?
transport delays idealised: model propagation through device or connection infinite frequency response. input pulse, no matter how short, produces output pulse. model ideal transmission line transport delay, example - , input changes propagate through line. transport delays can useful in testbenches queuing transactions on driver.
inertial delays approximate real-world delays. they're more complex but, in short, if try propagate pulse pulse width less propagation delay through device or wire, pulse disappears. inertial delays default in vhdl if can't see transport or inertial keyword.
at hdl level, actual difference between 2 in happens when schedule new transaction signal when signal has scheduled transactions. transport delays transactions queued up; inertial transactions simulator may merge them.
on verilog comment: bit of after-though in verilog (like else). however, delay on rhs of non-blocking assignment models transport delay:
always @(x) y <= #10 ~x; // transport continuous assignments don't queue transactions, model inertial delays:
assign #10 y = ~x; // inertial 
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