vhdl - Sum dynamic amount of vectors -

i have 2 vectors (type: integer, signed, unsigned, std_logic_vector, doesn't matter imlementation).

vector 1 has static size of 16 (equals 1word). vector 2 has dynamic size of x*16 (equals x words) x dynamic parameter.

now want have construct can sum x words vector 2 depending on parameter x.

sth. this:

vector_1 <= in 0 x generate              vector_2(x*16+15 downto x*16) +             end generate; 

anyone can imagine being possible in vhdl?

cheers, steffen

edit: maybe make more clear, want have:

accumulated_data <= std_logic_vector( signed(data_vector(0*16+15 downto 0*16)) +                                       signed(data_vector(1*16+15 downto 1*16)) +                                       ...                                                                              signed(data_vector(x*16+15 downto x*16))                                       ); 

x static @ synth.

for data_vector, use custom type, like:

type word_array_type array (integer range <>) of signed (15 downto 0); signal data_vector : word_array_type (2 downto 0); 

your sum more readable, like:

vector1 <= data_vector (0) + data_vector (1) + data_vector (2); 

the single-cycle code this:

process (clk)     variable sum : signed (vector1'range) := to_signed(0, vector1'length); begin     if (rising_edge(clk))         sum := to_signed(0, vector1'length);         in 0 (data_vector'length - 1) loop             sum := sum + data_vector(i);         end loop;         vector1 <= sum;     end if; end process; 

although tools interpret single cycle multi-input sum, may not.

however, adder 8 inputs going slow. approach this:

• a counter set stop once reaches x.
• an accumulator fed variable size multiplexer.
• multiplexer inputs connected vector 1 , vector 2, controlled counter.
• state machine or similar control accumulator, based on count (i.e. stop adding once x reached).