vhdl - Specman-simulator synchronization issue? -

i using cadence's ethernet evc wherein agent's monitor tapped @ following signals:

.            ____________                    _____ .clk   _____|            |__________________| .      ________ _______ ________________ _________ .data  __0a____x___07__x_______0b_______x_________ .                      ^ ^ 

it samples data @ rising , falling edges of clock. in example above, data 0x07 garbage data, , valid values 0xa (clk rise) , 0xb (clk fall). however, monitor sampling (for clk fall) 0x7!

i'm suspecting specman-simulator synchronization issue. how can resolved if is?

• simulator - ies 13.10

• irun 13.10 options - (i'll include here think relevant issue, plus i've no idea yet purpose is)

  -nomxindr   -vhdlsync   +neg_tchk   -nontcglitch   +transport_path_delays   -notimezeroasrtmsg   -pli_export   -snstubelab 

• languages - vhdl (top testbench), verilog (dut), specman (virtual sequence, enet , ocp evcs)

• time between 0x07 (left ^ in waveform above) , falling edge of clock (right ^) = 0.098ns

one colleague suggested using -sntimescale, still can't imagine how causing/would resolve issue. of these search strings not showing helpful hints, articles cadence: "specman tick synchronization delta delay timescale precision"

this indeed issue of timescale. there comprehensive cookbook talking deugging specman simulator interface synchronization issues. please take here.

to check timescale used in simulation, can add -print_hdl_precision option irun print precision vhdl hierarchy. verilog, printed automatically in case set either in code or via irun options. information printed during elaboration.

to check timescale used specman, can issue following command specman prompt:
sn> print get_timescale()

another option try (only after timescale option doesn't help) remove -vhdlsync flag. indeed in of mixed environments should add flag. there rare cases in environment works better without it. if try removing flag, remember re-elaborate.

if don't find solution problem in cookbook, deeper investigation should done. example, how specman samples signal. simple_port, event_port, tick access, etc.. trace , probe commands helpful. in such case, suggest contact cadence support.

good luck!
semadar